Reducing Defects in Patterning Processes
US-2015357196-A1 · Dec 10, 2015 · US
Tungsten salicide gate source for vertical NAND string to control on current and cell pillar fabrication
US8969948B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969948-B2 |
| Application number | US-201313852988-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 28, 2013 |
| Priority date | Mar 28, 2013 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
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A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. During fabrication of the memory device, a tungsten salicide is utilized as an etch-stop layer in place of a conventionally used aluminum oxide to form channel pillars having a high aspect ratio. Use of the tungsten salicide is useful for eliminating an undesired etch-stop recess and an undesired floating gate that is formed when an Al oxide etch-stop layer is conventionally used.
First claim
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The invention claimed is: 1. A memory device, comprising: a channel comprising a first end and a second end, the first end of the channel being coupled to a bit line and the second end of the channel being coupled to a source; a select gate formed at the second end of the channel to selectively control conduction between the bit line and the channel, the select gate comprising a layer of tungsten salicide; at least one non-volatile memory cell formed along a length of the chan…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P50/696Primary
Electricity · mapped topic
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- What does patent US8969948B2 cover?
- A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. During fabrication of the memory device, a tungsten salicide is utilized as an etch-stop layer in place of a conventionally used aluminum oxide to form channel pillars having a high aspect ratio. Use of the tungsten salicide is useful for eliminating an undesired etch-stop recess and an undesired…
- Who is the assignee on this patent?
- Simsek-Ege Fatma A, Parat Krishna K, Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification H10P50/696. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).