Semiconductor structure with flush shallow trench isolation and gate oxide and method of manufacturing the same
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Semiconductor device and method of fabricating the same
US8969939B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969939-B2 |
| Application number | US-201313960434-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 6, 2013 |
| Priority date | May 28, 2003 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
Official abstract text for this publication.
A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a semiconductor substrate: a semiconductor active region on a surface of the semiconductor substrate, wherein the semiconductor active region protrudes away from the surface of the semiconductor substrate; and an isolation layer on the surface of the semiconductor substrate to define the semiconductor active region, wherein the semiconductor active region protrudes beyond a surface of the isolation layer; wherein a fi…
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Classifications
Electricity · mapped topic
- H10W10/0145Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P10/00Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8969939B2 cover?
- A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding proces…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W10/0145. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).