Gate stack structure, semiconductor device and method for manufacturing the same

US8969930B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8969930-B2
Application numberUS-201113321886-A
CountryUS
Kind codeB2
Filing dateApr 6, 2011
Priority dateApr 7, 2010
Publication dateMar 3, 2015
Grant dateMar 3, 2015

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Abstract

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A gate stack structure comprises an isolation dielectric layer formed on and embedded into a gate. A sidewall spacer covers opposite side faces of the isolation dielectric layer, and the isolation dielectric layer located on an active region is thicker than the isolation dielectric layer located on a connection region. A method for manufacturing the gate stack structure comprises removing part of the gate in thickness, the thickness of the removed part of the gate on the active region is greater than the thickness of the removed part of the gate on the connection region so as to expose opposite inner walls of the sidewall spacer; forming an isolation dielectric layer on the gate to cover the exposed inner walls. There is also provided a semiconductor device and a method for manufacturing the same. The methods can reduce the possibility of short-circuit occurring between the gate and the second contact hole and can be compatible with the dual-contact-hole process.

First claim

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What is claimed is: 1. A gate stack structure, comprising: a gate dielectric layer formed on an active region and on a connection region in a substrate; a gate formed on the gate dielectric layer; and a sidewall spacer surrounding the gate dielectric layer and the gate; wherein the gate stack structure further comprising: an isolation dielectric layer formed on the gate, and wherein the sidewall spacer covers opposite side faces of the isolation dielectric layer, and the…

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What does patent US8969930B2 cover?
A gate stack structure comprises an isolation dielectric layer formed on and embedded into a gate. A sidewall spacer covers opposite side faces of the isolation dielectric layer, and the isolation dielectric layer located on an active region is thicker than the isolation dielectric layer located on a connection region. A method for manufacturing the gate stack structure comprises removing part …
Who is the assignee on this patent?
Yin Haizhou, Luo Zhijiong, Zhu Huilong, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10D64/01354. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).