Method and apparatus for selectively improving integrated device performance

Patent metadata

Field	Value
Publication number	US-8969166-B2
Application number	US-201414156785-A
Country	US
Kind code	B2
Filing date	Jan 16, 2014
Priority date	Apr 6, 2011
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

An apparatus for selectively improving integrated circuit performance is provided. In an example, an integrated circuit is fabricated according to an integrated circuit layout. A critical portion of the integrated circuit layout determines a speed of the integrated circuit, where at least a part of the critical portion includes at least one of a halo implant region, lightly doped drain (LDD) implant region, and source drain extension (SDE) implant region. A marker layer comprises the part of the critical portion that includes the at least one of the halo implant region, the lightly doped drain (LDD) implant region, and the source drain extension (SDE) implant region, and includes at least one transistor formed therefrom.

First claim

What is claimed is:

1. A method for selectively improving integrated circuit performance, comprising:
defining a critical portion of an integrated circuit layout that determines the speed of the integrated circuit;
identifying at least a part of the critical portion that includes a halo implant region;
performing a speed push flow process to increase performance of the part of the critical portion that includes the halo implant region;
wherein the speed push flow process fur…

Assignees

• Qualcomm Inc

Inventors

• Wang Zhongze
• Yeap Choh Fei
• Liu Ping

Classifications

• H10D84/0181

  Electricity · mapped topic

• H10D84/0167

  Electricity · mapped topic

• H10D84/0144

  Electricity · mapped topic

• H10D84/0128

  Electricity · mapped topic

• H10D84/85

  Electricity · mapped topic