Field-effect transistor (FET) with source-drain contact over gate spacer

Patent metadata

Field	Value
Publication number	US-8969152-B2
Application number	US-201313920044-A
Country	US
Kind code	B2
Filing date	Jun 17, 2013
Priority date	Jun 17, 2013
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

A field-effect transistor (FET) and methods for fabricating such. The FET includes a substrate having a crystalline orientation, a source region in the substrate, and a drain region in the substrate. Gate spacers are positioned over the source region and the drain region. The gate spacers include a gate spacer height. A source contact physically and electrically contacts the source region and extends beyond the gate spacer height. A drain contact physically and electrically contacts the drain region and extends beyond the gate spacer height. The source and drain contacts have the same crystalline orientation as the substrate.

First claim

What is claimed is:

1. A method for constructing a field-effect transistor (FET), the method comprising:
forming a source region and a drain region in a substrate;
forming gate spacers over the source region and the drain region, the gate spacers including a gate spacer height;
epitaxially growing a source contact and a drain contact, the source contact contacting the source region and extending beyond the gate spacer height, the drain contact contacting the drain region and e…

Assignees

• IBM

Inventors

• Chan Kevin K
• Haensch Wilfried E
• Leobandung Effendi
• Yang Min

Classifications

• H10D84/0186

  Electricity · mapped topic

• H10D84/0184

  Electricity · mapped topic

• H10D84/038

  Electricity · mapped topic

• H10D84/017 Primary

  Electricity · mapped topic

• H10D30/0223 Primary

  Electricity · mapped topic