Semiconductor device and method for manufacturing the same

US8969150B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8969150-B2
Application numberUS-201414324632-A
CountryUS
Kind codeB2
Filing dateJul 7, 2014
Priority dateMar 30, 2012
Publication dateMar 3, 2015
Grant dateMar 3, 2015

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Abstract

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A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n + -type semiconductor region and an anode p-type semiconductor region are formed in the semiconductor substrate and the second trench is formed so as to surround the n + -type semiconductor region in a planar view. A part of the anode p-type semiconductor region is formed directly below the n + -type semiconductor region, so that a PN junction is formed between the part of the anode p-type semiconductor region and the n + -type semiconductor region. Thereby a diode is formed. The dummy gate electrode is electrically coupled to one of an anode and a cathode.

First claim

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What is claimed is: 1. A method for manufacturing a semiconductor device including a trench gate type field effect transistor and a diode which are formed in a semiconductor substrate, the method comprising the steps of: (a) preparing the semiconductor substrate; (b) after the step (a), forming a first trench and a second trench in the semiconductor substrate; (c) after the step (b), forming a gate electrode of the trench gate type field effect transistor in the first trench t…

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What does patent US8969150B2 cover?
A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n + -type semiconductor region and an anode p-type semiconductor reg…
Who is the assignee on this patent?
Renesas Electronics Corp
What technology area does this patent fall under?
Primary CPC classification H10D64/513. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).