Systems and methods for a shared debug pin

Patent metadata

Field	Value
Publication number	US-8966313-B2
Application number	US-201213460796-A
Country	US
Kind code	B2
Filing date	Apr 30, 2012
Priority date	Apr 30, 2012
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

In some examples, a computer system includes a first component associated with a first power domain and a second component associated with a second power domain. The computer system also includes a debug port with a debug port pin shared by a debug operation pin of the first component and a corresponding debug operation pin of the second component. The computer system also includes a switch associated with the debug port pin to selectively isolate the debug operation pin of the first component from leakage current of the corresponding debug operation pin of the second component.

First claim

What is claimed is:

1. A computer system, comprising:
a first component associated with a first power domain of the computer system;
a second component associated with a second power domain of the computer system that is different than the first power domain;
a debug port with a debug port pin shared by a debug operation pin of the first component and a corresponding debug operation pin of the second component; and
a switch coupled to the debug port pin to isolate the debug operation pin of the first component from leakage current of the corresponding debug operation pin of the second component,
wherein the switch comprises a transistor positioned between a pull-up resistor or pull-down resistor and the debug operation pin of the second component.

2. The computer system of claim 1 , wherein the first component is a processor and the second component is an input/output (I/O) controller hub chipset.

3. The computer system of claim 1 , wherein the debug port pin shared by the debug operation pin of the first component and the corresponding debug operation pin of the second component corresponds to a test data in (TDI) signal pin.

4. The computer system of claim 1 , wherein the debug port pin shared by the debug operation pin of the first component and the corresponding debug operation pin of the second component corresponds to a test mode select (TMS) signal pin.

5. The computer system of claim 1 , wherein the debug port comprises an extended debug port (XDP) connector.

6. The computer system of claim 1 , wherein the switch selectively disconnects a test mode select (TMS) pin of the second component from a TMS pin of the first component based on a main power domain state of the computer system corresponding to the first power domain.

7. The computer system of claim 1 , wherein the switch selectively disconnects a test data in (TDI) pin of the second component from a TDI pin of the first component based on a main power domain state of the computer system.

8. The computer system of claim 1 , wherein the second component receives power from a standby power domain corresponding to the second power domain even when the computer system is turned off, and wherein the switch disconnects the debug operation pin of the first component from the corresponding debug operation pin of the second component in response to the computer system being turned off.

9. The computer system of claim 1 , wherein the second component receives power from a standby power domain corresponding to the second power domain even when the computer system is turned off, and wherein the switch connects the debug operation pin of the first component to the corresponding debug operation pin of the second component in response to the computer system being turned on.

10. The computer system of claim 1 , further comprising at least one additional switch, wherein each of the at least one additional switch selectively disconnects a different debug operation pin of the first component from a corresponding debug operation pin of the second component.

11. A method for a computer system, comprising:
sharing a debug port pin of a debug port by a debug operation pin of a first component and a corresponding debug operation pin of a second component, wherein the first component is associated with a first power domain of the computer system and the second component is associated with a second power domain of the computer system that is different than the first power domain; and
operating a switch coupled to the debug port pin to isolate the debug operation pin of the first component from leakage current of the corresponding debug operation pin of the second component when the second component is powered and the first component is not powered, the switch comprising a transistor positioned between a pull-up resistor or pull-down resistor and the debug operation pin of the second component.

12. The method of claim 11 , wherein operating the switch comprises operating the switch based on a main power domain state of the computer system.

13. The method of claim 11 , wherein operating the switch comprises disconnecting a test data in (TDI) signal pin of the first component from a corresponding TDI signal pin of the second component, or disconnecting a test model select (TMS) signal pin of the first component from a corresponding TMS signal pin of the second component.

14. The method of claim 11 , further comprising supplying power to an I/O controller hub chipset corresponding to the second component even when the computer system is off and operating the switch to disconnect the debug operation pin of a processor corresponding to the first component from the corresponding debug operation pin of the I/O controller hub chipset in response to the computer system being turned off.

15. The method of claim 12 , further comprising supplying power to an I/O controller hub chipset corresponding to the second component even when the computer system is off and operating the switch to connect the debug operation pin of a processor corresponding to the first component to the corresponding debug operation pin of the I/O controller hub chipset in response to the computer system being turned on.

16. A debug interface for a computer system, comprising:
a connector having a debug interface pin shared by a debug operation pin of a first component and a corresponding debug operation pin of a second component wherein the first component is associated with a first power domain of the computer system and the second component is associated with a second power domain of the computer system that is different than the first power domain; and
a switch coupled to the debug interface pin to isolate the debug operation in of the first component from leakage current of the corresponding debug operation pin of the second component when the second component is powered and the first component is not powered,
wherein the switch comprises a transistor positioned between a pull-up resistor or pull-down resistor and a debug operation pin of the second component.

17. The debug interface of claim 16 , wherein the switch is one of a plurality of switches associated with different debug interface pins of the connector shared by the first component and the second component, and wherein each of the plurality of switches operates to isolate the first component from leakage current of the second component when the second component is on and the first component is off.

18. The debug interface of claim 16 , wherein the debug interface pin corresponds to a test data in (TDI) pin and wherein the switch is placed between the TDI pin and the second component and is controlled by a main power domain status signal of the computer system.

19. The debug interface of claim 16 , wherein the debug interface pin corresponds to a test mode select (TMS) pin and wherein the switch is placed between the TMS pin and the second component and is controlled by a main power domain status signal of the computer system.

Assignees

• Truong Huong M
• Whiteman Jason W
• Patel Priti J
• Hewlett Packard Development Co

Inventors

• Truong Huong M
• Whiteman Jason W
• Patel Priti J

Classifications

• G06F11/3656 Primary

  using a specific debug interface · CPC title

• G06F11/2733

  Test interface between tester and unit under test · CPC title