Reduction in power supply induced jitter on a SerDes transmitter

Patent metadata

Field	Value
Publication number	US-8964880-B2
Application number	US-201213546635-A
Country	US
Kind code	B2
Filing date	Jul 11, 2012
Priority date	Jul 11, 2012
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

In an embodiment of the invention, a frequency divider in a phase-locked loop (PLL) circuit is provided power from the power supply that provides power to a transmission circuit. The PLL is configured to receive a first direct current (DC) reference voltage, a second DC voltage and a reference clock signal. The PLL is configured to generate a transmission clock signal. A transmission circuit is configured to receive the transmission clock signal, the second DC voltage and a data bus where the data bus includes a plurality of data bits in parallel. The transmission circuit transmits data serially.

First claim

What is claimed is:

1. A communication apparatus comprising:
a phase-locked loop (PLL) circuit, the PLL circuit including a frequency divider wherein the PLL circuit is configured to receive a first direct current (DC) reference voltage, a second DC voltage and a reference clock signal and wherein the PLL circuit is configured to generate a transmission clock signal;
a transmission circuit, the transmission circuit configured to receive the transmission clock signal, the second…

Assignees

• Ravinuthula Vishnu
• Rajapaksha Dushmantha
• Mair Hugh
• Texas Instruments Inc

Inventors

• Ravinuthula Vishnu
• Rajapaksha Dushmantha
• Mair Hugh

Classifications

• H03L7/18 Primary

  Electricity · mapped topic