Network processor unit and a method for a network processor unit

US8964594B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8964594-B2
Application numberUS-201414149029-A
CountryUS
Kind codeB2
Filing dateJan 7, 2014
Priority dateMay 30, 2008
Publication dateFeb 24, 2015
Grant dateFeb 24, 2015

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

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A method of and a network processor unit for processing of packets in a network, the network processor comprising: communication interface configured to receive and transmit packets; at least one processing means for processing packets or parts thereof; an embedded switch configured to switch packets between the communication interface and the processing means; and wherein the embedded switch is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means for processing thereof, to receive the processed first part of the packet from the processing means, and to transmit the processed first part of the packet.

First claim

Opening claim text (preview).

The invention claimed is: 1. A network processor unit for processing packets, the network processor unit comprising: an interface configured to receive and transmit packets; at least one processor for processing packets or parts of the packets; a switch configured to switch packets between the interface and the at least one processor; a traffic manager configured to communicate with the interface and the switch; and a buffer included in the switch, the buffer configured to…

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What does patent US8964594B2 cover?
A method of and a network processor unit for processing of packets in a network, the network processor comprising: communication interface configured to receive and transmit packets; at least one processing means for processing packets or parts thereof; an embedded switch configured to switch packets between the communication interface and the processing means; and wherein the embedded switch i…
Who is the assignee on this patent?
Marvell Int Ltd
What technology area does this patent fall under?
Primary CPC classification H04L47/32. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).