Multiple plane network-on-chip with master/slave inter-relationships
US-2015381707-A1 · Dec 31, 2015 · US
US8964559B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8964559-B2 |
| Application number | US-201313872450-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 29, 2013 |
| Priority date | Dec 21, 2009 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Aspects of the invention pertain to routing packets in a computer system while avoiding deadlock. A turn rule is set according to unique identifiers associated with switches in the system. Numeric values of switches in possible turns are compared to determine whether a turn is permissible. The rule applies to all nodes in the system. The rule may be violated when using virtual channels. Here, a violation is permissible when using monotonically increasing virtual channel numbers or monotonically decreasing virtual channel numbers. Alternatively, the violations of the turn rule may be allowed if they force a packet to change to a later virtual channel in some fixed ordering of virtual channels. Deadlock can thus be avoided in many different types of architectures, including mesh, torus, butterfly and flattened butterfly configurations.
Opening claim text (preview).
The invention claimed is: 1. A method of routing packets in a computer network to avoid deadlock, the method comprising: setting a turn rule for routing packets across the computer network, the turn rule prohibiting sending packets from a first switch (A) to a second switch (C) via an intermediate switch (B) given a value of a distinct identifier of the intermediate switch B in relation to values of distinct identifiers of both first switch A and second switch C; and providing t…
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