Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-8964487-B2
Application number	US-201213714953-A
Country	US
Kind code	B2
Filing date	Dec 14, 2012
Priority date	Dec 16, 2011
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

A semiconductor memory device includes a memory cell array having a plurality of bit lines and a plurality of word lines intersecting each other and a plurality of nonvolatile memory cells; and a page buffer for each bit line including a latch configured to store one of data to be written to a first nonvolatile memory cell selected by each word line and data read from the first nonvolatile memory cell, wherein before reading out data, the page buffer configured to store in a replica capacitor a voltage value of a word line adjacent to the selected word line when a second nonvolatile memory cell is turned on, the replica capacitor including a first capacitor and a second capacitor connected in parallel, and the page buffer is configured to vary when the latch judges the data from the first nonvolatile memory cell according to the voltage value.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array including a plurality of bit lines and a plurality of word lines intersecting each other and a plurality of nonvolatile memory cells at intersections of the bit lines and the word lines; and
a page buffer for each bit line including a latch configured to store one of data to be written to a nonvolatile memory cell selected by each word line and data read from the nonvolatile memory cell, wherein…

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hirano Makoto

Classifications

• G11C7/227

  Physics · mapped topic

• G11C16/32

  Physics · mapped topic

• G11C16/24 Primary

  Physics · mapped topic

• G11C16/0483

  Physics · mapped topic

• G11C16/26

  Physics · mapped topic