Apparatuses and methods for a multi-bit duty cycle monitor
US-11894044-B2 · Feb 6, 2024 · US
US8964484B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8964484-B2 |
| Application number | US-201213729153-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 28, 2012 |
| Priority date | Dec 28, 2012 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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A memory operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory. In the normal mode of operation, the memory can perform the asynchronous read operation, the page read operation, an asynchronous write operation in which a word of electronic data is stored into the memory that correspond to the address, or a page write operation in which a page electronic data is stored into the memory that correspond to the multiple addresses.
Opening claim text (preview).
What is claimed is: 1. A memory with integrated capabilities to measure read speed, comprising: a read speed counter configured to begin a counting process from a first state upon toggling of a first control line from a first logical value to a second logical value; a memory array configured to read a plurality of bits corresponding to an address upon the toggling of the first control line from the first logical value to the second logical value; an output latch configured to…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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