Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Semiconductor device and memory system
US8964483B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8964483-B2 |
| Application number | US-201213630702-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 28, 2012 |
| Priority date | Sep 30, 2011 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A semiconductor device is disclosed in which a plurality of memory cores are provided on a semiconductor chip. Each of the memory cores comprises: first and second circuit regions and a first and second through electrode groups. a first power supply is supplied in the first circuit region in which a data bus for parallel data is driven, and a second power supply separated from the first power supply is supplied in the second circuit region in which the parallel data and serial data are bidirectionally converted. The first through electrode group includes through electrodes supplying the first power supply to the first circuit region, and the second through electrode group includes through electrodes supplying the second power supply to the second circuit region.
First claim
Opening claim text (preview).
The invention claimed is: 1. A semiconductor device comprising: a first chip including first and second voltage terminals electrically independent of each other and a first data terminal, the first and second voltage terminals being supplied with first and second voltages, respectively; and a second chip stacked with the first chip, the second chip that includes: third and fourth voltage terminals electrically coupled to the first and second voltage terminals of the first chip,…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W70/60Primary
Electricity · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8964483B2 cover?
- A semiconductor device is disclosed in which a plurality of memory cores are provided on a semiconductor chip. Each of the memory cores comprises: first and second circuit regions and a first and second through electrode groups. a first power supply is supplied in the first circuit region in which a data bus for parallel data is driven, and a second power supply separated from the first power s…
- Who is the assignee on this patent?
- Ps4 Luxco Sarl
- What technology area does this patent fall under?
- Primary CPC classification H10W70/60. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).