Nonvolatile memory, electronic apparatus, and verification method

Patent metadata

Field	Value
Publication number	US-8964477-B2
Application number	US-201313856205-A
Country	US
Kind code	B2
Filing date	Apr 3, 2013
Priority date	Apr 11, 2012
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

A gate voltage generator which supplies first gate voltage at erase verify time to a first selected word line to which a first memory cell included in N memory cells is connected, which supplies the first gate voltage at the erase verify time to a second selected word line to which a first reference cell included in M reference cells is connected, which supplies second gate voltage at the erase verify time to a first non-selected word line connected to a memory cell array, and which supplies third gate voltage at the erase verify time to a second non-selected word line connected to a reference cell array is included. An electric current which flows through a reference cell connected to the second non-selected word line is stronger than an electric current which flows through a memory cell connected to the first non-selected word line.

First claim

What is claimed is:

1. A nonvolatile memory comprising:
a memory cell array having a first bit line connected to N memory cells;
a reference cell array having a second bit line connected to M reference cells, the M being smaller than the N;
a comparator which compares a first electric current which flows along the first bit line with a second electric current which flows along the second bit line; and
a gate voltage generator which supplies first gate voltage at erase verify…

Assignees

• Fujitsu Semiconductor Ltd

Inventors

• Tanaka Kengo

Classifications

• G11C16/28

  Physics · mapped topic

• G11C7/14 Primary

  Physics · mapped topic

• G11C16/3445

  Physics · mapped topic

• G11C16/30

  Physics · mapped topic

• G11C16/08

  Physics · mapped topic