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Memory cell string based on gated-diode cell and memory array using the same
US8964475B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8964475-B2 |
| Application number | US-201313912578-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 7, 2013 |
| Priority date | Jun 9, 2012 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Abstract
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The present invention provides a nonvolatile memory cell string and a memory array using the same. According to the present invention, a wall type semiconductor separated into twin fins and a memory cell string formed with memory cells having a gated diode structure along each fin are enabled to increase the degree of integration and basically prevent the interferences between adjacent cells. And a first semiconductor layer and a depletion region of a PN junction wrapped up by a gate electrode are enabled to remove GSL and CSL by GIDL memory operation and significantly increase the degree of integration for applying to a neuromorphic technology.
First claim
Opening claim text (preview).
What is claimed is: 1. A nonvolatile memory cell string comprising: two or more cell devices formed in series on a wall type semiconductor protruded from a semiconductor substrate with a predetermined length along one direction to form the cell string, wherein one end of the cell string is electrically connected to outside through one or more string selection transistors formed on one end of the wall type semiconductor, wherein each of the cell devices is formed on a first sem…
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Electricity · mapped topic
- G11C16/0408Primary
Physics · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8964475B2 cover?
- The present invention provides a nonvolatile memory cell string and a memory array using the same. According to the present invention, a wall type semiconductor separated into twin fins and a memory cell string formed with memory cells having a gated diode structure along each fin are enabled to increase the degree of integration and basically prevent the interferences between adjacent cells. A…
- Who is the assignee on this patent?
- Univ Seoul Nat R & Db Found
- What technology area does this patent fall under?
- Primary CPC classification G11C16/0408. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).