Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-8964472-B2
Application number	US-201314094300-A
Country	US
Kind code	B2
Filing date	Dec 2, 2013
Priority date	Jun 28, 2013
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers on a substrate, first vertical lines suitable for coupling bit lines, and second vertical lines suitable for coupling word lines of the memory blocks vertically stacked, wherein the memory blocks include selection lines vertically stacked and separated from each other, and the bit lines are coupled to the memory blocks and arranged in a plurality of layers.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a memory array including memory blocks stacked in a plurality of layers on a substrate;
first vertical lines suitable for coupling bit lines; and
second vertical lines suitable for coupling word lines of the memory blocks that are vertically stacked,
wherein the memory blocks include selection lines vertically stacked and separated from each other, and
wherein the bit lines are coupled to the memory blocks a…

Assignees

• Sk Hynix Inc

Inventors

• Aritome Seiichi

Classifications

• G11C16/0483

  Physics · mapped topic

• G11C16/0408 Primary

  Physics · mapped topic

• G11C16/3404 Primary

  Physics · mapped topic

• G11C16/10

  Physics · mapped topic

• G11C5/06 Primary

  Physics · mapped topic