Techniques for providing a direct injection semiconductor memory device

Patent metadata

Field	Value
Publication number	US-8964461-B2
Application number	US-201314084386-A
Country	US
Kind code	B2
Filing date	Nov 19, 2013
Priority date	Jul 27, 2009
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

Techniques for providing a direct injection semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device including the steps of applying a first non-negative voltage potential to a first region via a bit line and applying a second non-negative voltage potential to a second region via a source line. The method may also include applying a third voltage potential to a word line, wherein the word line may be spaced apart from and capacitively to a body region that may be electrically floating and disposed between the first region and the second region. The method may further include applying a fourth positive voltage potential to a third region via a carrier injection line, wherein the third region may be disposed below at least one of the first region, the body region, and the second region.

First claim

The invention claimed is:

1. A semiconductor memory device comprising:
a memory cell comprising:
a first region coupled to a bit line;
a second region coupled to a source line;
a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between and directly adjacent to the first region and the second region; and
a third region coupled to a carrier injection line, wherein the third region is disposed…

Assignees

• Micron Technology Inc

Inventors

• Luthra Yogesh

Classifications

• H10D30/711

  Electricity · mapped topic

• H10D10/00 Primary

  Electricity · mapped topic

• G11C5/02 Primary

  Physics · mapped topic

• G11C16/26 Primary

  Physics · mapped topic

• G11C11/402

  Physics · mapped topic