Circuit for digitizing a sum of signals

Patent metadata

Field	Value
Publication number	US-8963754-B2
Application number	US-201314022351-A
Country	US
Kind code	B2
Filing date	Sep 10, 2013
Priority date	Sep 10, 2012
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

A circuit for digitizing a sum of a first input signal and a plurality of second input signals has a passive adder that sums the second input signals and outputs a summation signal and a multi-bit quantizer circuit. The quantizer circuit compares the summation signal at a first comparator input with a signal at a second comparator input, which is derived from the first input signal and has an appropriate polarity so that the difference between the summation signal and the signal at the second comparator input is indicative of the sum of the first input signal and the plurality of second input signals. The comparator also produces a comparator output signal based on the sum of the first input signal and the plurality of second input signals. The quantizer circuit also has a control logic block for determining a multi-bit representation of the sum from the comparator output signal.

First claim

The invention claimed is:

1. A circuit for digitizing a sum of at least one first input signal and a plurality of second input signals comprising:
a passive adder circuit implemented with a first capacitor array and arranged for performing a summation of the plurality of second input signals and for outputting a summation signal;
a second capacitor array arranged for sampling the at least one first input signal, wherein at least one of the first capacitor array or the second cap…

Assignees

• Imec
• Stichting Imec Nederland
• Univ Leuven Kath
• Univ Leuven Kath

Inventors

• Morgado Alonso
• Porrazzo Serena
• Cannillo Francesco

Classifications

• H03M3/32 Primary

  Electricity · mapped topic

• H03M3/452

  Electricity · mapped topic

• H03M3/426 Primary

  Electricity · mapped topic