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Method for fabricating a carrier with a three dimensional inductor and structure thereof
US8963675B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8963675-B2 |
| Application number | US-201213644964-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 4, 2012 |
| Priority date | Jun 30, 2011 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Abstract
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A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist layer; forming a first dielectric layer on the protective layer; forming a second photoresist layer on the first dielectric layer; patterning the second photoresist layer to form a plurality of slots; forming a second metal layer in slots to form a plurality of inductive portions; removing the second photoresist layer; forming a second dielectric layer on the first dielectric layer; forming a third photoresist layer on the second dielectric layer; patterning the third photoresist layer to form a plurality of slots; and forming a third metal layer in slots.
First claim
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What is claimed is: 1. A carrier with a three dimensional inductor comprises: a substrate having a surface, at least one first bond pad and a protective layer, wherein the first bond pad is disposed on the surface, the protective layer is formed on the surface and comprises at least one first opening, and the first bond pad is exposed by the first opening; a first metal layer formed on the protective layer, the first metal layer comprises a first connecting pad and a plurality o…
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- What does patent US8963675B2 cover?
- A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist…
- Who is the assignee on this patent?
- Chipbond Technology Corp
- What technology area does this patent fall under?
- Primary CPC classification H05K1/165. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).