Clock signal initialization circuit and its method

Patent metadata

Field	Value
Publication number	US-8963591-B2
Application number	US-201314067519-A
Country	US
Kind code	B2
Filing date	Oct 30, 2013
Priority date	Oct 31, 2012
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

A clock signal initialization circuit capable of preventing the operating frequency of a semiconductor integrated circuit from exceeding the maximum permissible frequency determined based on the power consumption of that semiconductor integrated circuit even when the PLL circuit is in a transient state at the start-up is provided. A clock signal initialization circuit for a semiconductor integrated circuit that operates in synchronization with a clock signal generated by a PLL circuit, includes a controller that derives a clock signal having a frequency no greater than a maximum permissible frequency determined based on a power consumption of the semiconductor integrated circuit as a supply clock signal to the semiconductor integrated circuit at least until the PLL circuit becomes a locked state after power-on.

First claim

What is claimed is:

1. A clock signal initialization circuit comprising:
a PLL circuit that generates a clock signal and outputs the generated clock signal as an operation clock signal fora semiconductor integrated circuit, the generated clock signal being synchronized with an externally-supplied reference clock signal; and
a controller that derives a clock signal having a frequency no greater than a maximum permissible frequency determined based on a power consumption of the se…

Assignees

• Nec Corp

Inventors

• Yamashida Hisashi

Classifications

• H03L7/16

  Electricity · mapped topic

• G11C7/20 Primary

  Physics · mapped topic

• G11C7/222

  Physics · mapped topic

• G06F1/08

  Physics · mapped topic