Semiconductor device

US8963329B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8963329-B2
Application numberUS-201313915278-A
CountryUS
Kind codeB2
Filing dateJun 11, 2013
Priority dateJun 12, 2012
Publication dateFeb 24, 2015
Grant dateFeb 24, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a semiconductor device capable of increasing the number of signals. A semiconductor device according to an embodiment of the invention includes memories; a controller that designates addresses of the memories; a mounting board having lines formed thereon, the lines connecting the controller with the memories; and a first ball group that connects the controller with the lines of the mounting board. A plurality of address lines formed on the mounting board includes an address line formed of a front surface wiring layer, and an address line formed of a back surface wiring layer. In each of the front surface wiring layer and the back surface wiring layer, each of the address lines from first balls of the first ball group is routed in order from a first memory to a fourth memory.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: first to n-th (n is an integer equal to or greater than 2) memories; a controller that designates addresses of the n number of memories; a multi-layer wiring board having lines formed thereon, the lines connecting the controller with the memories; and a solder ball group including a plurality of solder balls arranged in an array, and connecting the controller with the lines of the multi-layer wiring board, wherein a…

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Frequently asked questions

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What does patent US8963329B2 cover?
Provided is a semiconductor device capable of increasing the number of signals. A semiconductor device according to an embodiment of the invention includes memories; a controller that designates addresses of the memories; a mounting board having lines formed thereon, the lines connecting the controller with the memories; and a first ball group that connects the controller with the lines of the …
Who is the assignee on this patent?
Renesas Electronics Corp
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).