Semiconductor device isolation structures

Patent metadata

Field	Value
Publication number	US-8963279-B2
Application number	US-201313769656-A
Country	US
Kind code	B2
Filing date	Feb 18, 2013
Priority date	Nov 28, 2006
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

Structures and methods are disclosed for the electrical isolation of semiconductor devices. A method of forming a semiconductor device may include providing a second integrated device region on a substrate that is spaced apart from a first integrated device region. An isolation region may be interposed between the first integrated device region and the second integrated device region. The isolation region may include an isolation recess that projects into the substrate to a first predetermined depth, and that may be extended to a second predetermined depth.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
an isolation region adjacent to a memory array region comprising a device recess, the isolation region including an isolation recess that includes a first interior side wall portion covered by a conformal dielectric, the conformal dielectric fully filling the device recess;
an extended recess including a second interior wall portion and a floor portion, the second interior wall portion and the floor portion of the extended recess being substantially covered by a second dielectric that is different from the conformal dielectric, wherein the extended recess extends into a substrate of the semiconductor memory device through a floor of the isolation recess; and
a dielectric filler, wherein the dielectric filler fully fills the isolation recess and the extended recess.

2. The semiconductor memory device of claim 1 , wherein the conformal dielectric fills the device recess separated from the isolation recess, and covers only the first interior wall portion of the isolation recess.

3. A semiconductor memory device, comprising:
an isolation region adjacent to a memory array region comprising a device recess, the isolation region including an isolation recess that includes a first interior side wall portion covered by a conformal dielectric, the conformal dielectric fully filling the device recess, wherein a depth of the device recess is less than a depth of the isolation recess;
an extended recess including a second interior wall portion and a floor portion, the second interior wall portion and the floor portion of the extended recess being substantially covered by a second dielectric that is different from the conformal dielectric; and
a dielectric filler, wherein the dielectric filler fully fills the isolation recess and the extended recess.

4. The semiconductor memory device of claim 3 , wherein the conformal dielectric fills the device recess separated from the isolation recess, and covers only the first interior wall portion of the isolation recess.

Assignees

• Micron Technology Inc

Inventors

• Sandhu Sukesh

Classifications

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/0143 Primary

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D62/115 Primary

  Dielectric isolations, e.g. air gaps · CPC title

• H01L21/76229

  Electricity · mapped topic