Semiconductor device and high frequency switch
US-2024321773-A1 · Sep 26, 2024 · US
Semiconductor device and method for manufacturing semiconductor device
US8963246B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8963246-B2 |
| Application number | US-201113583409-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 9, 2011 |
| Priority date | Mar 9, 2010 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Abstract
Official abstract text for this publication.
There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
First claim
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The invention claimed is: 1. A semiconductor device that serves as a sensor formed on an SOI substrate for X-ray detection, comprising: the SOI substrate including a second-conductive-type semiconductor layer having first and second regions each being on one surface of the second-conductive-type semiconductor layer, the first and second regions being adjacent each other on the one surface of the second-conductive-type semiconductor layer, an oxide film layer having one surface…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8963246B2 cover?
- There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlaye…
- Who is the assignee on this patent?
- Arai Yasuo, Okihara Masao, Kasai Hiroki, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H10D86/201. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).