Semiconductor device and driver circuit with drain and isolation structure interconnected through a diode circuit, and method of manufacture thereof
US-2015380317-A1 · Dec 31, 2015 · US
P-channel LDMOS transistor and method of producing a p-channel LDMOS transistor
US8963243B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8963243-B2 |
| Application number | US-201113807287-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 24, 2011 |
| Priority date | Jul 1, 2010 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Abstract
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The p-channel LDMOS transistor comprises a semiconductor substrate ( 1 ), an n well ( 2 ) of n-type conductivity in the substrate, and a p well ( 3 ) of p-type conductivity in the n well. A portion of the n well is located under the p well. A drain region ( 4 ) of p-type conductivity is arranged in the p well, and a source region ( 9 ) of p-type conductivity is arranged in the n well. A gate dielectric ( 7 ) is arranged on the substrate, and a gate electrode ( 8 ) is arranged on the gate dielectric. A body contact region ( 14 ) of n-type conductivity is arranged in the n well. A p implant region ( 17 ) is arranged in the n well under the p well in the vicinity of the p well. The p implant region locally compensates n-type dopants of the n well.
First claim
Opening claim text (preview).
The invention claimed is: 1. A p-channel LDMOS transistor, comprising: a semiconductor substrate; an n well of n-type conductivity in the substrate; a p well of p-type conductivity in the n well, a portion of the n well being located under the p well; a drain region of p-type conductivity in the p well; a gate dielectric on the substrate; a gate electrode on the gate dielectric; a source region of p-type conductivity in the n well; a body contact region of n-type con…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
- H10D62/371Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8963243B2 cover?
- The p-channel LDMOS transistor comprises a semiconductor substrate ( 1 ), an n well ( 2 ) of n-type conductivity in the substrate, and a p well ( 3 ) of p-type conductivity in the n well. A portion of the n well is located under the p well. A drain region ( 4 ) of p-type conductivity is arranged in the p well, and a source region ( 9 ) of p-type conductivity is arranged in the n well. A gate di…
- Who is the assignee on this patent?
- Park Jong Mun, Knaipp Martin, Ams Ag
- What technology area does this patent fall under?
- Primary CPC classification H10D62/371. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).