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Three dimensional semiconductor memory devices and methods of fabricating the same
US8963231B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8963231-B2 |
| Application number | US-201213401013-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 21, 2012 |
| Priority date | Mar 29, 2011 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Abstract
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Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.
First claim
Opening claim text (preview).
What is claimed is: 1. A device, comprising: an electrode structure including an alternating stack of electrodes and insulating patterns on a semiconductor substrate; a vertical active pattern extending through the alternating stack, at least one specific electrode of the electrode structure having first and second outer sidewalls opposite respective inner sidewalls that face the vertical active pattern; a recessed region penetrating at least the specific electrode and filled…
Assignees
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D30/63Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8963231B2 cover?
- Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating laye…
- Who is the assignee on this patent?
- Lee Sunghae, Eom Daehong, Kim Jingyun, and 8 more
- What technology area does this patent fall under?
- Primary CPC classification H10D30/63. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).