Semiconductor device

US8963207B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8963207-B2
Application numberUS-201414188462-A
CountryUS
Kind codeB2
Filing dateFeb 24, 2014
Priority dateFeb 25, 2013
Publication dateFeb 24, 2015
Grant dateFeb 24, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a buffer layer, a channel layer and a barrier layer formed over a substrate, a trench penetrating through the barrier layer to reach the middle of the channel layer, and a gate electrode disposed inside the trench via a gate insulating film. The channel layer contains n-type impurities, and a region of the channel layer positioned on a buffer layer side has an n-type impurity concentration larger than a region of the channel layer positioned on a barrier layer side, and the buffer layer is made of nitride semiconductor having a band gap wider than that of the channel layer. The channel layer is made of GaN and the buffer layer is made of AlGaN. The channel layer has a channel lower layer containing n-type impurities at an intermediate concentration and a main channel layer formed thereon and containing n-type impurities at a low concentration.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a first nitride semiconductor layer formed over a substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and made of nitride semiconductor having a band gap wider than that of the second nitride semiconductor layer; a trench penetrating through the third nitride semiconductor layer to reach a…

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What does patent US8963207B2 cover?
A semiconductor device includes a buffer layer, a channel layer and a barrier layer formed over a substrate, a trench penetrating through the barrier layer to reach the middle of the channel layer, and a gate electrode disposed inside the trench via a gate insulating film. The channel layer contains n-type impurities, and a region of the channel layer positioned on a buffer layer side has an n-…
Who is the assignee on this patent?
Renesas Electronics Corp
What technology area does this patent fall under?
Primary CPC classification H10D62/60. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).