Tunable fin-SCR for robust ESD protection

Patent metadata

Field	Value
Publication number	US-8963201-B2
Application number	US-201213411667-A
Country	US
Kind code	B2
Filing date	Mar 5, 2012
Priority date	Mar 5, 2012
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.

First claim

What is claimed is:

1. A silicon-controlled-rectifier (SCR) disposed on a substrate, comprising:
a longitudinal silicon fin extending between a single anode and a single cathode and including a junction region there between;
one or more first transverse fins that traverse the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region; and
one or more second transverse fins that traverse the longitudinal fin at one or more respective tapping points positioned between the junction region and the cathode;
wherein at least one of the one or more first transverse fins and at least one of the one or more second transverse fins are spaced apart from one another along the longitudinal fin between the single anode and the single cathode and traverse the longitudinal fin by crossing the longitudinal fin and residing on both sides thereof.

2. The SCR of claim 1 , wherein at least one of the one or more first transverse fins is in close proximity to the anode.

3. The SCR of claim 1 , wherein at least one of the one or more second transverse fins is in close proximity to the cathode.

4. The SCR of claim 1 , wherein the one or more first and second transverse fins are coupled together to form an electric field control tap of the SCR.

5. The SCR of claim 1 , further comprising:
a gate dielectric adjacent to the junction region;
a conductive gate electrode adjacent to the gate dielectric and electrically isolated from the longitudinal fin via the gate dielectric, wherein the conductive gate electrode is spaced apart from the one or more first transverse fins; and
a voltage bias circuit to apply a voltage bias to the conductive gate electrode.

6. The SCR of claim 1 , wherein the one or more first transverse fins have respective fin lengths that are larger near the anode region and the respective fin lengths decrease near the junction region.

7. The SCR of claim 1 , wherein at least one of the one or more first transverse fins comprise respective metal fins which overlie the longitudinal fin at respective tapping points and which are in direct electrical contact with the longitudinal fin at the respective tapping points.

8. The SCR of claim 1 , wherein at least one of the one or more first transverse fins are made of silicon and include respective distal end regions having respective doping concentrations that are higher than a doping concentration of the longitudinal fin between the junction region and the cathode.

9. The SCR of claim 1 , wherein the substrate comprises a bulk silicon substrate.

10. The SCR of claim 1 , wherein the substrate comprises a silicon-on-insulator (SOI) substrate.

11. The SCR of claim 1 , wherein the longitudinal fin has a length between the anode and cathode that is less than a total distance between the anode and cathode, such that a single longitudinal fin does not extend continuously between the anode and cathode.

12. The SCR of claim 1 , further comprising: at least one additional longitudinal fin in parallel with the longitudinal fin extending between the anode and cathode.

13. A semiconductor device, comprising:
a longitudinal fin comprised of silicon and including:
a first distal region having a first conductivity type;
a first inner region contacting the first distal region at a first junction and having a second conductivity type;
a second inner region contacting the first inner region at a second junction and having the first conductivity type; and
a second distal region contacting the second inner region at a third junction and having the second conductivity type; and

a first transverse fin that traverses the longitudinal fin at the first inner region;
wherein the first transverse fin extends outwardly in opposite directions from opposing sidewalls of the longitudinal fin.

14. The semiconductor device of claim 13 , wherein:
the first distal region has a first doping concentration;
the first inner region has a second doping concentration;
the second inner region has a third doping concentration which is less than the first doping concentration; and
the second distal region has a fourth doping concentration which is greater than the second doping concentration.

15. The semiconductor device of claim 13 , wherein the semiconductor device is structured to enable and disable current flow between the first and second distal regions based on whether a voltage bias applied to the first transverse fin has a predetermined relationship with a predetermined threshold voltage.

16. The semiconductor device of claim 13 , wherein the first transverse fin is a metal body that overlies and is in direct electrical contact with the first inner region of the longitudinal fin.

17. The semiconductor device of claim 13 , wherein the first transverse fin is a silicon body traversing the longitudinal fin.

18. The semiconductor device of claim 17 , wherein the first transverse fin comprises:
a first transverse distal region extending away from a first sidewall of the longitudinal fin in a first direction, the first transverse distal region having the first conductivity type at a fifth doping concentration which is greater than the third doping concentration;
a first transverse inner region extending in the first direction and having the second conductivity type at a sixth doping concentration, wherein the sixth doping concentration is less than the fifth doping concentration;
a second transverse distal region extending away from a second sidewall of the longitudinal fin in a second direction, the second transverse distal region having the first conductivity type at a fifth doping concentration which is greater than the third doping concentration; and
a second transverse inner region extending in the second direction and having the second conductivity type at a sixth doping concentration, wherein the sixth doping concentration is less than the fifth doping concentration.

19. The semiconductor device of claim 13 , further comprising:
a second transverse fin that traverses the longitudinal fin at the first inner region and spaced apart from the first transverse fin,
wherein the second transverse fin traverse the longitudinal fin by crossing the longitudinal fin and residing on both sides thereof, and
wherein the first distal region comprises a single anode and the second distal region comprises a single cathode.

20. The semiconductor device of claim 13 , further comprising:
a third transverse fin that traverses the longitudinal fin at the second inner region.

21. The semiconductor device of claim 13 , further comprising:
a gate dielectric adjacent to the second junction region;
a conductive gate electrode adjacent to the gate dielectric and electrically isolated from the longitudinal fin via the gate dielectric; and
a voltage bias circuit to apply a voltage bias to the conductive gate.

22. A semiconductor device, comprising:
a longitudinal fin comprised of silicon and including:
a first distal region having a first conductivity type;
a first inner region contacting the first distal region at a first junction and having a second conductivity type;
a second inner region contacting the first inner region at a second junction and having the first conductivity type; and
a second distal region contacting the second inner region at a third junction and having the second conductivity type; and

a first transverse fin that traverses the longitudinal fin at the first inner region;

Assignees

• Shrivastava Mayank
• Russ Christian
• Gossner Harald
• Intel Mobile Comm Gmbh

Inventors

• Shrivastava Mayank
• Russ Christian
• Gossner Harald

Classifications

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D89/713

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H10D62/206

  Cathode base regions of thyristors · CPC title

• H10D62/199

  Anode base regions of thyristors · CPC title

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title