Static random access memory device with stacked fets
US-2024431087-A1 · Dec 26, 2024 · US
US8963199B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8963199-B2 |
| Application number | US-201213985552-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 21, 2012 |
| Priority date | Mar 18, 2011 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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An N type well (NW) is formed over a prescribed depth from a main surface of a semiconductor substrate (SUB), and a P type well (PW) and an N type drain region (ND) are formed in the N type well (NW). An N type source region (NS), an N+ type source region (NNS), and a P+ type impurity region (BCR) are formed in the P type well (PW). The N type source region (NS) is formed on a region situated directly below the N+ type source region (NNS), and not on a region situated directly below the P+ type impurity region (BCR), and the P+ type impurity region (BCR) is in direct contact with the P type well (PW).
Opening claim text (preview).
The invention claimed is: 1. A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a main surface; a first impurity region of the first conductivity type formed over a prescribed depth from said main surface of said semiconductor substrate, and having a first impurity concentration; a second impurity region of a second conductivity type formed over a prescribed depth from a surface of said first impurity region to be surrounded by sai…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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