Thin film transistor and manufacturing method therefor, array substrate, and display device
US-11869976-B2 · Jan 9, 2024 · US
Thin film transistor substrate and method of manufacturing the same
US8963154B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8963154-B2 |
| Application number | US-201313755730-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 31, 2013 |
| Priority date | Aug 10, 2012 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Abstract
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A thin film transistor substrate includes a base substrate, an active pattern disposed on the base substrate, a gate insulation pattern disposed on the active pattern, a gate electrode disposed on the gate insulation pattern and overlapping the channel, and a light-blocking pattern disposed between the base substrate and the active pattern and having a size greater than the active pattern. The active pattern includes a source electrode, a drain electrode, and a channel disposed between the source electrode and the drain electrode.
First claim
Opening claim text (preview).
What is claimed is: 1. A thin film transistor substrate comprising: a base substrate; an active pattern on the base substrate and comprising a source electrode, a drain electrode, and a channel between the source electrode and the drain electrode; a gate insulation pattern on the active pattern; a gate electrode on the gate insulation pattern and overlapping the channel; and a light-blocking pattern between the base substrate and the active pattern, and having a planar siz…
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D30/0314Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8963154B2 cover?
- A thin film transistor substrate includes a base substrate, an active pattern disposed on the base substrate, a gate insulation pattern disposed on the active pattern, a gate electrode disposed on the gate insulation pattern and overlapping the channel, and a light-blocking pattern disposed between the base substrate and the active pattern and having a size greater than the active pattern. The …
- Who is the assignee on this patent?
- Samsung Display Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D30/0314. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).