Display apparatus
US-2024414942-A1 · Dec 12, 2024 · US
Thin film transistor, method of manufacturing the same, and image display device equipped with thin film transistor
US8963147B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8963147-B2 |
| Application number | US-201113876419-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 21, 2011 |
| Priority date | Sep 28, 2010 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Abstract
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A thin film transistor includes, on an insulating substrate, at least: a gate electrode; a gate insulating layer; a source electrode; a drain electrode; a metal oxide layer including a semiconductor region and an insulating region, each of the semiconductor region and the insulating region being composed of a same metal oxide material; and an insulating protective layer. The semiconductor region includes a region between the source electrode and the drain electrode, and is overlaid on a part of each of them. The semiconductor region is formed between the gate insulating layer and the insulating protective layer to abut on at least one of them. The electric conductivity of the semiconductor region is higher than that of the insulating region.
First claim
Opening claim text (preview).
The invention claimed is: 1. A thin film transistor comprising, on an insulating substrate, at least: a gate electrode; a gate insulating layer; a source electrode; a drain electrode; a metal oxide layer including a semiconductor region and an insulating region, each of the semiconductor region and the insulating region being composed of a same metal oxide material; and an insulating protective layer, wherein: the semiconductor region includes a region between the so…
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Classifications
Electricity · mapped topic
- H10D30/6755Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8963147B2 cover?
- A thin film transistor includes, on an insulating substrate, at least: a gate electrode; a gate insulating layer; a source electrode; a drain electrode; a metal oxide layer including a semiconductor region and an insulating region, each of the semiconductor region and the insulating region being composed of a same metal oxide material; and an insulating protective layer. The semiconductor regio…
- Who is the assignee on this patent?
- Imamura Chihiro, Miyairi Yukari, Koyama Hiroaki, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).