Manufacturing method of circuit board

US8963019B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8963019-B2
Application numberUS-201213570251-A
CountryUS
Kind codeB2
Filing dateAug 9, 2012
Priority dateJun 11, 2012
Publication dateFeb 24, 2015
Grant dateFeb 24, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A circuit board and a manufacturing method thereof are provided. According to the method, a dielectric layer is formed on a dielectric substrate, and the dielectric layer contains active particles. A surface treatment is performed on a surface of the dielectric first conductive layer is formed on the activated surface of the dielectric layer. A conductive via is formed in the dielectric substrate and the dielectric layer. A patterned mask layer is formed on the first conductive layer, in which the patterned mask layer exposes the conductive via and a part of the first conductive layer. A second conductive layer is formed on the first conductive layer and conductive via exposed by the patterned mask layer. The patterned mask layer and the first conductive layer below the patterned mask layer are removed.

First claim

Opening claim text (preview).

What is claimed is: 1. A manufacturing method of circuit board, comprising: providing a dielectric substrate; forming a dielectric layer on the dielectric substrate, wherein the dielectric layer contains a plurality of active particles therein; performing a surface treatment on a surface of the dielectric layer so as to activate the active particles at the surface of the dielectric layer; forming a first conductive layer on the activated surface of the dielectric layer; fo…

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What does patent US8963019B2 cover?
A circuit board and a manufacturing method thereof are provided. According to the method, a dielectric layer is formed on a dielectric substrate, and the dielectric layer contains active particles. A surface treatment is performed on a surface of the dielectric first conductive layer is formed on the activated surface of the dielectric layer. A conductive via is formed in the dielectric substra…
Who is the assignee on this patent?
Yu Cheng-Po, Huang Shang-Feng, Lee Chang-Ming, and 2 more
What technology area does this patent fall under?
Primary CPC classification H05K3/381. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).