Manufacturing method for semiconductor structure
US-12165910-B2 · Dec 10, 2024 · US
Semiconductor device and method of manufacturing the same
US8962444B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8962444-B2 |
| Application number | US-201314053913-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 15, 2013 |
| Priority date | Oct 15, 2012 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Abstract
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Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively.
First claim
Opening claim text (preview).
What is claimed: 1. A method of manufacturing a semiconductor device comprising: forming a poly-silicon layer doped with first p-type dopants on a substrate; etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench; forming a device isolation pattern in the trench; thermally treating the poly-silicon pattern in a first gas comprising second p-type dopants; forming a dielectric layer and a conductive layer on the thermally treated poly-si…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W10/014Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8962444B2 cover?
- Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon patter…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd, Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W10/014. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).