Method of making a semiconductor layer having at least two different thicknesses

US8962399B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8962399-B2
Application numberUS-201414177593-A
CountryUS
Kind codeB2
Filing dateFeb 11, 2014
Priority dateFeb 11, 2013
Publication dateFeb 24, 2015
Grant dateFeb 24, 2015

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Abstract

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A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for producing a semiconductor layer having at least two different thicknesses (TSi1, TSi2) from a stack of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method comprising at least a sequence comprising the following steps: etching of the first semiconductor layer so that the first semiconductor layer is continuous and comprises a…

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What does patent US8962399B2 cover?
A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a…
Who is the assignee on this patent?
Commissariat Energie Atomique, St Microelectronics Crolles 2, St Microelectronics Sa, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10P90/1912. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).