Electronic package module and method for fabrication of the same
US-2024413067-A1 · Dec 12, 2024 · US
Fabrication method of carrier-free semiconductor package
US8962396B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8962396-B2 |
| Application number | US-201314086135-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 21, 2013 |
| Priority date | Mar 10, 2011 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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- Title
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Abstract
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A carrier-free semiconductor package includes a circuit structure having an insulating layer and a circuit layer embedded in the insulating layer and having a plurality of conductive traces and RF (radio frequency) traces, a chip disposed on a first surface of the insulating layer and electrically connected to the conductive traces, an encapsulant covering the chip and the circuit layer, a ground layer formed on a second surface of the insulating layer opposite to the first surface, and a plurality of solder balls disposed on the conductive traces or terminals on the conductive traces, wherein portions of the solder balls electrically connect the ground layer so as to allow the RF traces and the ground layer to form a microstrip line having an RF function, thus obtaining a single-layer carrier-free semiconductor package having low cost and simplified RF design.
First claim
Opening claim text (preview).
What is claimed is: 1. A fabrication method of a carrier-free semiconductor package, comprising the steps of: forming on a carrier a circuit layer having a plurality of conductive traces and RF traces; forming an insulating layer on the carrier and the circuit layer, wherein the insulating layer has a plurality of openings for exposing the conductive traces, respectively, and has a first surface in contact with the carrier and a second surface opposite to the first surface; re…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8962396B2 cover?
- A carrier-free semiconductor package includes a circuit structure having an insulating layer and a circuit layer embedded in the insulating layer and having a plurality of conductive traces and RF (radio frequency) traces, a chip disposed on a first surface of the insulating layer and electrically connected to the conductive traces, an encapsulant covering the chip and the circuit layer, a grou…
- Who is the assignee on this patent?
- Siliconware Precision Industries Co Ltd, Siliconware Precision Industries Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W74/117. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).