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Method of fabricating a wafer level chip scale package without an encapsulated via
US8962391B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8962391-B2 |
| Application number | US-201314091040-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 26, 2013 |
| Priority date | Oct 22, 2008 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Abstract
Official abstract text for this publication.
An improved wafer level chip scale packaging technique is described which does not use an encapsulated via to connect between a redirection layer and a pad within the pad ring on the semiconductor die. In an embodiment, a first dielectric layer is formed such that it terminates on each die within the die's pad ring. Tracks are then formed in a conductive layer which contact one of the pads and run over the edge of an opening onto the surface of the first dielectric layer. These tracks may be used to form an electrical connection between the pad and a solder ball.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method of fabricating a packaged semiconductor device, comprising: forming a first dielectric layer on an active face of a semiconductor wafer comprising an array of semiconductor die, wherein each semiconductor die comprises a plurality of pads arranged in a pad ring around the periphery of the die on an active face of the die and wherein the first dielectric layer comprises a first region terminated on each die within the pad ring and a further reg…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W74/129Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8962391B2 cover?
- An improved wafer level chip scale packaging technique is described which does not use an encapsulated via to connect between a redirection layer and a pad within the pad ring on the semiconductor die. In an embodiment, a first dielectric layer is formed such that it terminates on each die within the die's pad ring. Tracks are then formed in a conductive layer which contact one of the pads and …
- Who is the assignee on this patent?
- Cambridge Silicon Radio Ltd, Cambridge Silicon Radio Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W74/129. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).