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Microelectronic packages including patterned die attach material and methods for the fabrication thereof
US8962389B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8962389-B2 |
| Application number | US-201313906161-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 30, 2013 |
| Priority date | May 30, 2013 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Abstract
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Embodiments of microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the fabrication method includes printing a patterned die attach material onto the backside of a wafer including an array of non-singulated microelectronic die each having an interior keep-out area, such as a central keep-out area. The die attach material, such as a B-stage epoxy, is printed onto the wafer in a predetermined pattern such that the die attach material does not encroaching into the interior keep-out areas. The wafer is singulated to produce singulated microelectronic die each including a layer of die attach material. The singulated microelectronic die are then placed onto leadframes or other package substrates with the die attach material contacting the package substrates. The layer of die attach material is then fully cured to adhere an outer peripheral portion of the singulated microelectronic die to its package substrate.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for fabricating a plurality of microelectronic packages, the method comprising: printing a patterned die attach material onto the backside of a wafer including an array of non-singulated microelectronic die each having an interior keep-out area, the patterned die attach material not encroaching into the interior keep-out areas of the array of non-singulated microelectronic die; after printing the patterned die attach material onto the backside of…
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Classifications
Operations & Transport · mapped topic
Operations & Transport · mapped topic
- B81C1/00261Primary
Operations & Transport · mapped topic
- B81C1/00325Primary
Operations & Transport · mapped topic
Operations & Transport · mapped topic
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- What does patent US8962389B2 cover?
- Embodiments of microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the fabrication method includes printing a patterned die attach material onto the backside of a wafer including an array of non-singulated microelectronic die each having an interior keep-out area, such as a central keep-out area. The die attach material, such as a B-sta…
- Who is the assignee on this patent?
- Stermer Jr William C, Bowles Philip H, Magnus Alan J, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification B81C1/00261. Mapped technology areas include Operations & Transport.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).