Integration of a titania layer in an anti-reflective coating

Patent metadata

Field	Value
Publication number	US-8962374-B2
Application number	US-201213534037-A
Country	US
Kind code	B2
Filing date	Jun 27, 2012
Priority date	Jun 27, 2012
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

A stack of a first anti-reflective coating (ARC) layer and a titanium layer is formed on a front surface of a semiconductor substrate including a p-n junction, and is subsequently patterned so that a semiconductor surface is physically exposed in metal contact regions of the front surface of the semiconductor substrate. The remaining portion of the titanium layer is converted into a titania layer by oxidation. A metal layer is plated on the metal contact regions, and a copper line is subsequently plated on the metal layer or a metal semiconductor alloy derived from the metal layer. A second ARC layer is deposited over the titania layer and the copper line, and is subsequently patterned to provide electrical contact to the copper line.

First claim

What is claimed is:

1. A method of forming an anti-reflective coating comprising:
providing a semiconductor substrate;
forming a stack comprising forming a first dielectric material layer on an entire topmost surface of said semiconductor substrate and forming a titanium layer directly on a topmost surface of said first dielectric material layer, wherein an entirety of a bottommost surface of said titanium layer contacts an entire topmost surface of said first dielectric material layer;
patterning said stack to physically expose a semiconductor surface of said semiconductor substrate and to provide a patterned stack, from bottom to top, of a remaining portion of said first dielectric material layer and a remaining portion of said titanium layer;
converting said remaining portion of said titanium layer of said patterned stack into a titania layer by oxidation;
plating at least one metallic material directly on a topmost surface of said exposed semiconductor surface while preventing growth of said at least one metallic material on a topmost surface of said titania layer; and
forming a second dielectric material layer directly on a topmost surface of said titania layer and over at least a portion of said at least one metallic material, wherein said first dielectric material layer, said titania layer, and said second dielectric material layer collectively form an anti-reflective coating.

2. The method of claim 1 , further comprising:
forming a metal semiconductor alloy portion by reacting a first metallic material of said at least one metallic material with a semiconductor material underneath said semiconductor surface.

3. The method of claim 2 , further comprising plating a second metallic material directly on said metal semiconductor alloy portion while preventing growth of said second metallic material from said titania layer.

4. The method of claim 2 , further comprising plating, before said forming of said metal semiconductor alloy portion, a second metallic material directly on said first metallic material while preventing growth of said second metallic material from said titania layer.

5. The method of claim 2 , further comprising plating copper on one of said first metallic material and said metallic semiconductor alloy portion while preventing growth of copper from said titania layer.

6. The method of claim 1 , wherein said at least one metallic material comprises a first metallic material and a second metallic material, and said method further comprises:
plating said first metallic material on said semiconductor surface while preventing growth of said first metallic material from said titania layer, wherein said first metallic material does not overlie said titania layer;
converting said first metallic material into a metal semiconductor alloy portion; and
plating said second metallic material on said metal semiconductor alloy portion while preventing growth of said second metallic material from said titania layer, wherein said second metallic material overlies an edge portion of said titania layer.

7. The method of claim 1 , wherein said at least one metallic material comprises a first metallic material and a second metallic material, and said method further comprises:
plating said first metallic material on said semiconductor surface while preventing growth of said first metallic material from said titania layer, wherein said first metallic material does not overlie said titania layer;
plating said second metallic material on said first semiconductor material while preventing growth of said second metallic material from said titania layer, wherein said second metallic material overlies an edge portion of said titania layer; and
converting said first metallic material into a metal semiconductor alloy portion.

8. The method of claim 1 , wherein said first dielectric material layer comprises silicon nitride, and said second dielectric material layer comprises a material selected from silicon nitride, silicon oxide, and magnesium oxide.

9. The method of claim 1 , further including forming a p-n junction within said semiconductor substrate at a location vertically offset from said semiconductor surface prior to forming said first dielectric material layer.

10. A method of forming an anti-reflective coating comprising:
providing a semiconductor substrate;
forming a stack comprising forming a first dielectric material layer on an entire topmost surface of said semiconductor substrate and forming a titania layer directly on a topmost surface of said first dielectric material layer;
patterning said stack to physically expose a topmost surface of said semiconductor substrate, wherein said patterning comprises removing said titania layer from a first portion of said stack to physically expose an underlying portion of said first dielectric layer, while maintaining said titania layer within a second portion of said stack, and wet etching said exposed underlying portion of said first dielectric material layer;
plating at least one metallic material directly on a topmost surface of said exposed semiconductor surface while preventing growth of said at least one metallic material on a topmost surface of said titania layer; and
forming a second dielectric material layer directly on a topmost surface of said titania layer and over at least a portion of said at least one metallic material, wherein said first dielectric material layer, said titania layer, and said second dielectric material layer collectively form an anti-reflective coating.

11. The method of claim 10 , wherein said removing said titania layer from a first portion of said stack is performed by irradiation by laser.

12. The method of claim 11 , further comprising selectively deepening a p-n junction in said semiconductor substrate only in regions irradiated by said laser.

13. The method of claim 1 , wherein said semiconductor substrate comprises a semiconductor material, and wherein a top surface of said semiconductor substrate is a faceted surface.

14. The method of claim 13 , wherein said semiconductor material is a single crystalline semiconductor material and said faceted surface is formed by contacting the top surface of said semiconductor substrate with a base solution.

15. The method of claim 13 , wherein said semiconductor material is a polycrystalline semiconductor material and said faceted surface is formed by contacting said top surface of said semiconductor substrate with an acid solution.

16. The method of claim 1 , wherein said oxidation is a thermal oxidation performed at a temperature from 250° C. to 600° C.

17. The method of claim 16 , wherein said oxidation is performed in oxygen, water, and an oxygen/water mixture.

Assignees

• Papa Rao Satyavolu S
• Fisher Kathryn C
• Hovel Harold J
• Huang Qiang
• Huang Susan
• Kim Young-Hee
• IBM

Inventors

• Papa Rao Satyavolu S
• Fisher Kathryn C
• Hovel Harold J
• Huang Qiang
• Huang Susan
• Kim Young-Hee

Classifications

• H10F77/703

  of the semiconductor bodies, e.g. textured active layers · CPC title

• H10F77/211

  for photovoltaic cells · CPC title

• H10F71/121

  The active layers comprising only Group IV materials · CPC title

• H10F10/14

  Photovoltaic cells having only PN homojunction potential barriers · CPC title

• H10F71/00

  Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title