Semiconductor device and fabrication method thereof
US-12159906-B2 · Dec 3, 2024 · US
Lattice matched crystalline substrates for cubic nitride semiconductor growth
US8961687B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8961687-B2 |
| Application number | US-55143009-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 31, 2009 |
| Priority date | Aug 31, 2009 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Abstract
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Disclosed embodiments include methods of fabricating a semiconductor layer or device and devices fabricated thereby. The methods include, but are not limited to, providing a substrate having a cubic crystalline surface with a known lattice parameter and growing a cubic crystalline group III-nitride alloy layer on the cubic crystalline substrate by coincident site lattice matched epitaxy. The cubic crystalline group III-nitride alloy may be prepared to have a lattice parameter (a′) that is related to the lattice parameter of the substrate (a). The group III-nitride alloy may be a cubic crystalline In x Ga y Al 1-x-y N alloy. The lattice parameter of the In x Ga y Al 1-x-y N or other group III-nitride alloy may be related to the substrate lattice parameter by (a′)=√2(a) or (a′)=(a)/√2. The semiconductor alloy may be prepared to have a selected band gap.
First claim
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What is claimed is: 1. A method of fabricating a semiconductor layer comprising: providing a substrate having a cubic crystalline surface with a known lattice parameter (a); and growing a cubic crystalline group III-nitride alloy layer on the cubic crystalline substrate surface by coincident site lattice matched epitaxy, wherein the cubic crystalline group III-nitride alloy is prepared to have a lattice parameter (a′) that is related to the lattice parameter (a) wherein (a′) is…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P14/3416Primary
Electricity · mapped topic
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- What does patent US8961687B2 cover?
- Disclosed embodiments include methods of fabricating a semiconductor layer or device and devices fabricated thereby. The methods include, but are not limited to, providing a substrate having a cubic crystalline surface with a known lattice parameter and growing a cubic crystalline group III-nitride alloy layer on the cubic crystalline substrate by coincident site lattice matched epitaxy. The cu…
- Who is the assignee on this patent?
- Norman Andrew G, Ptak Aaron J, Mcmahon William E, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10P14/3416. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).