Data cache block deallocate requests

Patent metadata

Field	Value
Publication number	US-8959289-B2
Application number	US-201213655699-A
Country	US
Kind code	B2
Filing date	Oct 19, 2012
Priority date	Mar 28, 2012
Publication date	Feb 17, 2015
Grant date	Feb 17, 2015

Abstract

A data processing system includes a processor core supported by upper and lower level caches. In response to executing a deallocate instruction in the processor core, a deallocation request is sent from the processor core to the lower level cache, the deallocation request specifying a target address associated with a target cache line. In response to receipt of the deallocation request at the lower level cache, a determination is made if the target address hits in the lower level cache. In response to determining that the target address hits in the lower level cache, the target cache line is retained in a data array of the lower level cache and a replacement order field in a directory of the lower level cache is updated such that the target cache line is more likely to be evicted from the lower level cache in response to a subsequent cache miss.

First claim

What is claimed is:

1. A method of data processing in a data processing system including a processor core supported by upper and lower level caches, the method comprising:
the processor core executing a deallocate instruction at completion of processing of a dataset including a target cache line and a plurality of other cache lines to promote eviction of the dataset from the lower level cache;
in response to executing the deallocate instruction in the processor core, sending a d…

Assignees

• IBM

Inventors

• Ghai Sanjeev
• Guthrie Guy L
• Starke William J
• Stuecheli Jeff A
• Williams Derek E
• Williams Phillip G

Classifications

• G06F12/0804

  Physics · mapped topic

• G06F12/0815 Primary

  Physics · mapped topic

• G06F12/126 Primary

  Physics · mapped topic

• G06F12/0897

  Physics · mapped topic

• G06F12/0811

  Physics · mapped topic