System and method for accessing memory

Patent metadata

Field	Value
Publication number	US-8959271-B2
Application number	US-201313835864-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Feb 17, 2015
Grant date	Feb 17, 2015

Abstract

A close proximity memory arrangement maintains a point to point association between DQs, or data lines, to DRAM modules employs a clockless state machine on a DRAM side of the memory controller-DRAM interface such that a single FIFO on the memory controller side synchronizes or orders the DRAM fetch results. Addition of a row address (ROW-ADD) and column address (COL-ADD) strobe reducing latency and power demands. Close proximity point to point DRAM interfaces render the DRAM side FIFO redundant in interfaces such as direct stacked 3D DRAMs on top of the logic die hosting the memory controller. The close proximity point to point arrangement eliminates the DRAM internal FIFO and latency scheme, resulting in just the memory controller internal clock domain crossing FIFOs.

First claim

What is claimed is:

1. A method of accessing memory comprising:
positioning a memory component in close proximity and in point to point connection to a corresponding controller;
issuing a read request from the controller to the memory component, the read request traversing a memory interface between the controller and the memory component, the memory interface having a memory side and a controller side;
transferring results of the read request to the memory interface via a clo…

Assignees

• Intel Corp

Inventors

• Schaefer Andre

Classifications

• G11C7/1072 Primary

  Physics · mapped topic

• G11C7/10

  Physics · mapped topic

• G11C7/109

  Physics · mapped topic

• G11C11/4076

  Physics · mapped topic