Semiconductor integrated circuit

Patent metadata

Field	Value
Publication number	US-8958264-B2
Application number	US-201314044861-A
Country	US
Kind code	B2
Filing date	Oct 2, 2013
Priority date	May 12, 2011
Publication date	Feb 17, 2015
Grant date	Feb 17, 2015

Abstract

There are included first and second dynamic circuits and first and second transistors. The first dynamic circuit keeps a first dynamic node at a first level when a plurality of input signals is in a first state, and switches the first dynamic node between the first level and a second level in accordance with a first clock signal when the plurality of input signals is in a second state. The second dynamic circuit includes a compensating circuit that is provided between the second dynamic node and a second power supply and connects the second dynamic node to the second power supply so as to compensate the level of the second dynamic node when the plurality of input signals is in the second state and the first dynamic node is at a level other than the first level.

First claim

What is claimed is:

1. A semiconductor integrated circuit comprising:
a first dynamic circuit for receiving a plurality of input signals and a first clock signal and controlling a level of a first dynamic node;
a first transistor provided between a second dynamic node and a first power supply, for being conduction controlled in accordance with the level of the first dynamic node;
a second transistor provided between the second dynamic node and the first power supply so as to b…

Assignees

• Panasonic Corp

Inventors

• Koike Tsuyoshi
• Narumi Noriaki

Classifications

• H03K19/0963 Primary

  Electricity · mapped topic

• G11C8/10 Primary

  Physics · mapped topic

• H03K17/223

  Electricity · mapped topic