Output buffer and semiconductor device

Patent metadata

Field	Value
Publication number	US-8957708-B2
Application number	US-201313946603-A
Country	US
Kind code	B2
Filing date	Jul 19, 2013
Priority date	Jul 25, 2012
Publication date	Feb 17, 2015
Grant date	Feb 17, 2015

Abstract

An output buffer has a first transistor and a voltage mitigation second transistor. The first transistor is configured to generate a voltage value corresponding to the power-supply voltage in response to an input signal. The second transistor is provided between an output line and the first transistor. A gate terminal of the second transistor is applied with a power-supply bias voltage which turns the second transistor on and makes a voltage between gate and source terminals of the second transistor constant in accordance with a power-supply voltage.

First claim

What is claimed is:

1. An output buffer that is configured to output an output signal via an output line in response to an input signal, the output signal having a voltage value corresponding to a power-supply voltage, the output buffer comprising:
a first MOS transistor that has a source terminal thereof applied with the power-supply voltage and a gate terminal thereof supplied with the input signal;
a second MOS transistor that has a drain terminal thereof connected to the out…

Assignees

• Lapis Semiconductor Co Ltd

Inventors

• Miyazaki Masahiro
• Hashidate Shuichi

Classifications

• G05F1/10 Primary

  Physics · mapped topic

• H03K19/018585

  Electricity · mapped topic

• H03K19/018521 Primary

  Electricity · mapped topic