Systems and methods for sensing current while minimizing measurement error and power loss
US-2015331049-A1 · Nov 19, 2015 · US
Startup of DC-DC converters utilizing multiple power segments
US8957657B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8957657-B2 |
| Application number | US-201213621380-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 17, 2012 |
| Priority date | Sep 16, 2011 |
| Publication date | Feb 17, 2015 |
| Grant date | Feb 17, 2015 |
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Abstract
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Generally, this disclosure provides methods and systems for improved startup for DC-DC converters that reduce input voltage droop, in-rush current and output voltage jumps. The system may include a power stage circuitry including a plurality of power segments coupled in parallel, the power stage circuitry is coupled between an input voltage and output stage circuitry and configured to deliver power to a load coupled to the output stage circuitry. The system may further include PWM and power stage controller circuitry configured to sequentially and progressively activate the plurality of power segments to limit an input in-rush current from the input voltage during a ramp up period and output voltage at the output stage circuitry.
First claim
Opening claim text (preview).
What is claimed is: 1. A DC-DC converter system, comprising: power stage circuitry comprising a plurality of power segments coupled in parallel, said power stage circuitry is coupled between an input voltage and output stage circuitry and configured to deliver power to a load coupled to said output stage circuitry; and pulse width modulation (PWM) and power stage controller circuitry configured to sequentially and progressively activate said plurality of power segments to limit…
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Frequently asked questions
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- What does patent US8957657B2 cover?
- Generally, this disclosure provides methods and systems for improved startup for DC-DC converters that reduce input voltage droop, in-rush current and output voltage jumps. The system may include a power stage circuitry including a plurality of power segments coupled in parallel, the power stage circuitry is coupled between an input voltage and output stage circuitry and configured to deliver p…
- Who is the assignee on this patent?
- Fairchild Semiconductor
- What technology area does this patent fall under?
- Primary CPC classification G05F1/46. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).