Flat panel display and method of manufacturing the same

US8957421B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8957421-B2
Application numberUS-201213680781-A
CountryUS
Kind codeB2
Filing dateNov 19, 2012
Priority dateAug 20, 2012
Publication dateFeb 17, 2015
Grant dateFeb 17, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In a flat panel display (FPD) and a method of manufacturing the same, the FPD includes a substrate, a semiconductor layer formed on the substrate, a wiring line formed on the substrate so as to be separated from the semiconductor layer, an insulating layer formed on the semiconductor layer and the wiring line, a gate electrode formed on the insulating layer formed on the semiconductor layer and extended to a top of the wiring line, and a source electrode and a drain electrode coupled to a source region and a drain region, respectively, of the semiconductor layer. Capacitance is formed by the gate electrode and the wiring line.

First claim

Opening claim text (preview).

What is claimed is: 1. A flat panel display (FPD) device, comprising: a substrate; a semiconductor layer formed on the substrate; a wiring line formed on the substrate so as to be separated from the semiconductor layer; an insulating layer formed on the semiconductor layer and the wiring line; a gate electrode formed on the insulating layer, the gate electrode continuously and completely overlying the wiring line which is formed on the semiconductor layer, and extended to…

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What does patent US8957421B2 cover?
In a flat panel display (FPD) and a method of manufacturing the same, the FPD includes a substrate, a semiconductor layer formed on the substrate, a wiring line formed on the substrate so as to be separated from the semiconductor layer, an insulating layer formed on the semiconductor layer and the wiring line, a gate electrode formed on the insulating layer formed on the semiconductor layer and…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D86/441. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).