Method for manufacturing semiconductor thick metal structure

US8956972B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8956972-B2
Application numberUS-201214351828-A
CountryUS
Kind codeB2
Filing dateOct 12, 2012
Priority dateOct 14, 2011
Publication dateFeb 17, 2015
Grant dateFeb 17, 2015

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Abstract

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A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti—TiN laminated structure is used as an anti-reflection layer to implement 4 μm metal etching without residue. In the metal patterning step, N 2 is used for the protection of a sidewall to implement on a 4 μm metal concave-convex structure a tilt angle of nearly 90 degrees, and a main over-etching step is added to implement the smoothness of the sidewall of the 4 μm metal concave-convex structure. A half-filled passivation filling structure is used to implement effective passivation protection of 1.5 um metal gaps having less than 4 um of metal thickness. Manufacturing of the 4 μm thick metal structure having a linewidth/gap of 1.5 μm/1.5 μm is finally implemented.

First claim

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What is claimed is: 1. A method of manufacturing of a semiconductor thick metal structure, comprising: a thick metal deposition step comprising: depositing a barrier layer, a metal layer, and an anti-reflection layer on a surface of a semiconductor chip, wherein the metal layer has a thickness of 3.5 μm to 4.5 μm; the anti-reflection layer comprises a titanium layer and a titanium nitride layer; a metal patterning step comprising: coating a photoresist layer on the anti-reflecti…

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What does patent US8956972B2 cover?
A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti—TiN laminated structure is used as an anti-reflection layer to implement 4 μm metal etching without residue. In the metal patterning step, N 2 is used for the protection of a sidewall to implement on a…
Who is the assignee on this patent?
Csmc Technologies Fab1 Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W20/031. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).