Method of storing data in non-volatile memory having multiple planes, non-volatile memory controller therefor, and memory system including the same

Patent metadata

Field	Value
Publication number	US-8954708-B2
Application number	US-201213617507-A
Country	US
Kind code	B2
Filing date	Sep 14, 2012
Priority date	Dec 27, 2011
Publication date	Feb 10, 2015
Grant date	Feb 10, 2015

Abstract

A method of controlling a non-volatile memory device having multiple planes including receiving write requests from a host, the write requests each including a logical address, a write command, and a data set; storing the data sets at an address of a buffer; storing the buffer address in a mapping table that maps addresses of the buffer to the multiple planes; sequentially transmitting the data sets stored at respective buffer addresses to page buffers, respectively, of the planes corresponding to the buffer addresses according to the mapping table; and programming in parallel at least two data sets stored in respective page buffers to memory cells of the non-volatile memory device.

First claim

What is claimed is:

1. A method of controlling a non-volatile memory device including multiple planes, the method comprising:
receiving at least one write request from a host, the at least one write request including a plurality of data sets, each of the plurality of data sets including at least one page of data;
storing the plurality of data sets at buffer addresses in a buffer;
storing the buffer addresses in a mapping table, the mapping table being configured to map the buffer addresses to the multiple planes;
sequentially transmitting, according to the mapping table, the plurality of data sets stored at respective ones of the buffer addresses to page buffers of the multiple planes corresponding to the buffer addresses; and
programming, in parallel, at least two of the plurality of data sets from the page buffers to memory cells of the non-volatile memory device.

2. The method of claim 1 , wherein the multiple planes include at least two planes.

3. The method of claim 1 , wherein the at least one write request is a random write request.

4. The method of claim 1 , wherein
a number of the plurality of data sets sequentially transmitted to the page buffers is the same as a number of the multiple planes, if a number of the plurality of data sets stored in the buffer is at least equal to the number of the multiple planes, and
the programming simultaneously programs the plurality of data sets to the memory cells if a number of the plurality of data sets stored in the respective page buffers equals the number of the multiple planes.

5. The method of claim 1 , further comprising:
setting a start time if a data set among the plurality of data sets received from the host and stored in the buffer corresponds to a desired plane among the multiple planes; and
checking whether a time limit from the start time has been reached.

6. The method of claim 5 , further comprising:
performing a multi-plane program operation on a number of the plurality of data sets, which is less than a number of the multiple planes, if a number of the plurality of data sets stored in the buffer is less than the number of the multiple planes after reaching the time limit.

7. The method of claim 6 , wherein the performing the multi-plane program operation on the number of the plurality of data sets, which is less than the number of the multiple planes, comprises:
sequentially storing data sets among the number of the plurality of data sets in respective page buffers of corresponding planes of the non-volatile memory device; and
programming, in parallel, valid data sets from among the data sets stored in the page buffers, and at least one invalid data set stored in at least one page buffer of at least one uncorresponding plane, in the memory cells.

8. The method of claim 6 , wherein the performing the multi-plane program operation on the number of the plurality of data sets, which is less than the number of the multiple planes, comprises:
sequentially storing, in page buffers of corresponding planes of the non-volatile memory device, as many data sets as a maximum number of available planes from among the plurality of data sets stored in the buffer;
programming, in parallel, as many of the plurality of data sets as the maximum number of available planes in the memory cells;
storing, in a page buffer of a corresponding plane of the non-volatile memory device, a remaining data set, from among the plurality of data sets, remaining in the buffer; and
programming the remaining data set stored in the page buffer, wherein
the maximum number of available planes is a maximum number of available planes that are simultaneously programmable by the non-volatile memory device, and
the maximum number is a value less than the number of the plurality of data sets stored in the buffer.

9. The method of claim 1 , wherein the mapping table stores a buffer address corresponding to each of the multiple planes and the mapping table is updated if a data set is stored in the buffer.

10. A non-transitory computer-readable medium storing a program which, when executed by a computer, performs the method of claim 1 .

11. A method of controlling a non-volatile memory device including multiple planes, the method comprising:
storing, in a buffer, a number of valid pages of data, the number of valid pages of data corresponding to a number of the multiple planes of the non-volatile memory device;
storing buffer addresses in a mapping table, the buffer addresses corresponding to a storage location of the valid pages of data, the mapping table configured to map the buffer addresses to the multiple planes; and
performing a multi-plane program operation on the valid pages of data stored at the buffer addresses according to the mapping table.

12. The method of claim 11 , wherein the performing the multi-plane program operation comprises:
sequentially transmitting the valid pages of data from the buffer to respective page buffers of the multiple planes; and
simultaneously programming the valid pages of data in the page buffers based on a physical address associated with the valid pages of data.

13. A memory system comprising:
a buffer memory;
a non-volatile memory device including multiple planes; and
a memory controller configured to,
receive a plurality of write requests, each of the plurality of write requests including a logical address and a data set from a host,
store the data sets in the buffer memory in response to the plurality of write requests, the data sets having corresponding logical addresses included in the plurality of write requests, the logical addresses being non-sequential,
sequentially transmit the data sets from the buffer memory to respective page buffers of the multiple planes, and
perform a multi-plane program operation to program the data sets in the respective page buffers to the non-volatile memory device.

14. The memory system of claim 13 , wherein the memory controller comprises:
a mapping table including buffer address information corresponding to each of the multiple planes.

15. The memory system of claim 14 , wherein
the multiple planes include four planes, each of the four planes including one of a first, second, third, and fourth pages,
the memory controller is configured to control a first of the data sets, the first of the data sets corresponding to a first of the logical addresses to be stored in the first page;
the memory controller is configured to control a second of the data sets, the second of the data sets corresponding to a second of the logical addresses to be stored in the second page;
the memory controller is configured to control a third of the data sets, the third of the data sets corresponding to a third of the logical addresses to be stored in the third page;
the memory controller is configured to control a fourth of the data sets, the fourth of the data sets corresponding to a fourth of the logical addresses to be stored in the fourth page; and
at least two logical addresses among the first through the fourth logical addresses are non-sequential.

16. The memory system of claim 15 , wherein
the memory controller is configured to sequentially transmit the first through fourth data sets from the buffer memory to the respective page buffers of the multiple planes with reference to the mapping table; and

the first through fourth data sets stored in the respective page buffers are simultaneously programmed to the first through fourth pages, respectively.

17. The memory system of claim 13 , wherein the memory controller is configured to perfo

Assignees

• Kim Jin Yeong
• Hong Du-Won
• Samsung Electronics Co Ltd

Inventors

• Kim Jin Yeong
• Hong Du-Won

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G06F13/14

  Handling requests for interconnection or transfer · CPC title

• G06F12/02 Primary

  Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title