Semiconductor gas sensor device and manufacturing method thereof
US-2015377813-A1 · Dec 31, 2015 · US
Electronic device and its manufacturing method
US8952467B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8952467-B2 |
| Application number | US-201314046423-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 4, 2013 |
| Priority date | Oct 19, 2012 |
| Publication date | Feb 10, 2015 |
| Grant date | Feb 10, 2015 |
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Abstract
Official abstract text for this publication.
An electronic device includes a substrate, a sidewall that is disposed on the substrate and forms a cavity, a first layer that is disposed on the sidewall and covers the cavity, a second layer that is formed on the first layer and has a region disposed outside an outline of the first layer in a plan view, a dielectric layer disposed below the region of the second layer disposed outside the outline of the first layer in a plan view, and a functional element disposed inside the cavity.
First claim
Opening claim text (preview).
What is claimed is: 1. An electronic device comprising: a substrate; a sidewall that is disposed on the substrate and forms a cavity; a first layer that is disposed on the sidewall and covers the cavity; a second layer that is formed on the first layer and has a region disposed outside an outline of the first layer in a plan view, the first layer and the second layer having common through holes penetrating to the cavity; a dielectric layer disposed below the region of the…
Assignees
Inventors
Classifications
- B81C1/00333Primary
Operations & Transport · mapped topic
Operations & Transport · mapped topic
- B81B7/0058Primary
Operations & Transport · mapped topic
Operations & Transport · mapped topic
Operations & Transport · mapped topic
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Frequently asked questions
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- What does patent US8952467B2 cover?
- An electronic device includes a substrate, a sidewall that is disposed on the substrate and forms a cavity, a first layer that is disposed on the sidewall and covers the cavity, a second layer that is formed on the first layer and has a region disposed outside an outline of the first layer in a plan view, a dielectric layer disposed below the region of the second layer disposed outside the outl…
- Who is the assignee on this patent?
- Seiko Epson Corp
- What technology area does this patent fall under?
- Primary CPC classification B81C1/00333. Mapped technology areas include Operations & Transport.
- When was this patent published?
- Publication date Tue Feb 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).