Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices

Patent metadata

Field	Value
Publication number	US-8952460-B2
Application number	US-201314077918-A
Country	US
Kind code	B2
Filing date	Nov 12, 2013
Priority date	Nov 18, 2011
Publication date	Feb 10, 2015
Grant date	Feb 10, 2015

Abstract

A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate comprising a germanium containing region and an adjoining silicon containing region, wherein an upper surface of said germanium containing region is coplanar with an upper surface of said silicon containing region;
a first gate structure on a channel region of said germanium containing region and comprising:
a first silicon oxide layer that is in direct contact with an upper surface of said germanium containing region, a second silicon oxide layer of a substantially uniform thickness having a 1 sigma non-uniformity of less than 0.2 Å that is in direct contact with said first silicon oxide layer, at least one first high-k gate dielectric layer in direct contact with said second silicon oxide layer, and at least one first gate conductor in direct contact with said at least one first high-k gate dielectric layer, wherein said upper surface of said germanium containing region is substantially free of germanium oxide, and a source region and a drain region on opposing sides of said channel region of said germanium containing region; and

a second gate structure on a channel region of said silicon containing region and comprising:
a first silicon oxide layer that is in direct contact with an upper surface of said silicon containing region, a second silicon oxide layer of a substantially uniform thickness having a 1 sigma non-uniformity of less than 0.2 Å that is in direct contact with said first silicon oxide layer, at least one second high-k gate dielectric layer in direct contact with said second silicon oxide layer, and at least one second gate conductor in direct contact with said at least one second high-k gate dielectric layer, and a source region and a drain region on opposing sides of said channel region of said silicon containing region.

2. The semiconductor device of claim 1 , wherein a portion of said silicon containing region extends beneath a bottommost surface of said germanium containing region.

3. The semiconductor device of claim 1 , wherein said second silicon oxide layer has a thickness ranging from 0.1 nm to 0.8 nm.

4. The semiconductor device of claim 1 , wherein said germanium containing region contains greater than 25% germanium.

5. The semiconductor device of claim 1 , wherein said germanium containing region contains greater than 99% germanium.

6. The semiconductor device of claim 1 , wherein said germanium containing region comprises 100% germanium.

7. The semiconductor device of claim 2 , wherein said germanium containing region has a same crystal orientation as said portion of said silicon region that extends beneath said bottommost surface of said germanium containing region.

Assignees

• IBM

Inventors

• Brodsky Maryjane
• Chowdhury Murshed M
• Chudzik Michael P
• Dai Min
• Krishnan Siddarth A
• Narasimha Shreesh
• Siddiqui Shahab

Classifications

• H10D64/01356 Primary

  the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence) · CPC title

• H10D84/856

  the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D64/68

  characterised by the insulator, e.g. by the gate insulator · CPC title

• H10D30/0223

  having source and drain regions or source and drain extensions self-aligned to sides of the gate · CPC title