Semiconductor device, method of manufacturing the same, and electronic device including the semiconductor device

Patent metadata

Field	Value
Publication number	US-8952356-B2
Application number	US-201113292285-A
Country	US
Kind code	B2
Filing date	Nov 9, 2011
Priority date	Mar 30, 2011
Publication date	Feb 10, 2015
Grant date	Feb 10, 2015

Abstract

An example embodiment relates to a semiconductor device including a semiconductor element. The semiconductor element may include a plurality of unit layers spaced apart from each other in a vertical direction. Each unit layer may include a patterned graphene layer. The patterned graphene layer may be a layer patterned in a nanoscale. The patterned graphene layer may have a nanomesh or nanoribbon structure. The semiconductor device may be a transistor or a diode. An example embodiment relates to a method of making a semiconductor device including a semiconductor element.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor element on a substrate including,
a plurality of unit layers, the plurality of unit layers spaced apart from each other in a vertical direction with respect to a surface of the substrate and stacked in the vertical direction between the surface of the substrate and a gate electrode, the plurality of unit layers including first and second unit layers, each of the plurality of unit layers including a patterned graphene layer, the patterned graphene layer including one of a nanomesh structure and a nanoribbon structure, and
an insulation layer between every two adjacent unit layers, the insulation layer including a first insulation single layer between the first and second unit layers, the first and second unit layers directly contacting lower and upper surfaces of the first insulation single layer, respectively, the first insulation single layer filling a substantially entire space between the first and second unit layers.

2. The semiconductor device of claim 1 , wherein
a width of a pattern of the patterned graphene layer is in the range from about 2 nm to about 10 nm.

3. The semiconductor device of claim 1 , wherein
the semiconductor device is a transistor, and
the semiconductor element is a channel layer.

4. The semiconductor device of claim 3 , wherein
the transistor includes one of a single-gate and a double-gate structure.

5. The semiconductor device of claim 1 , wherein
the semiconductor device is a diode,
the diode includes a first layer combined with a second layer, and
the first layer includes the semiconductor element.

6. The semiconductor device of claim 5 , wherein
the second layer is a semiconductor layer.

7. The semiconductor device of claim 5 , wherein
the second layer is a metal layer.

8. An electronic device comprising the semiconductor device of claim 1 .

9. The electronic device of claim 8 , wherein
the electronic device is one of a display device and a photoelectronic device.

10. The electronic device of claim 8 , wherein the semiconductor device is included in one of a switching device, a driving device, and a sensing device.

11. A method of manufacturing a semiconductor device, comprising:
forming a semiconductor element on an underlying substrate by,
forming a plurality of unit layers, the plurality of unit layers spaced apart from each other in a vertical direction with respect to a surface of the underlying substrate and stacked in the vertical direction between the surface of the underlying substrate and a gate electrode, the plurality of unit layers including first and second unit layers, each of the plurality of unit layers including a patterned graphene layer, the patterned graphene layer including one of a nanomesh structure and a nanoribbon structure, and
forming an insulation layer between every two adjacent unit layers, the insulation layer including a first insulation single layer between the first and second unit layers, the first and second unit layers directly contacting lower and upper surfaces of the first insulation single layer, respectively, the first insulation single layer filling a substantially entire space between the first and second unit layers.

12. The method of claim 11 , wherein the forming of the semiconductor element comprises:
forming a first patterned graphene layer on a first substrate;
transferring the first patterned graphene layer from the first substrate to the underlying substrate;
forming a first insulation layer on the first patterned graphene layer; and
forming a second patterned graphene layer on the first insulation layer.

13. The method of claim 12 , wherein the forming a second patterned graphene layer on the first insulation layer comprises:
preparing the second patterned graphene layer on a third substrate, and
transferring the second pattern graphene layer on the first insulation layer after the preparing the second patterned graphene layer.

14. The method of claim 12 , further comprising:
forming a second insulation layer on the second patterned graphene layer; and
forming a third patterned graphene layer on the second insulation layer.

15. The method of claim 12 , wherein the underlying substrate includes a flexible substrate.

16. The method of claim 11 , wherein the forming of the semiconductor element comprises:
forming a first patterned graphene layer on a first substrate;
forming a first insulation layer on the first patterned graphene layer; and
forming a second patterned graphene layer on the first insulation layer.

17. The method of claim 16 , further comprising:
forming a second insulation layer on the second patterned graphene layer; and
forming a third patterned graphene layer on the second insulation layer.

18. The method of claim 11 , wherein
the patterned graphene layer includes one of a nanomesh and a nanoribbon structure.

19. The method of claim 11 , further comprising:
forming a source contacting a first region of the semiconductor element;
forming a drain contacting a second region of the semiconductor element; and
forming a gate configured to apply an electric field to the semiconductor element.

20. The method of claim 11 , wherein
the semiconductor element is a first layer, and
the method further includes forming a second layer contacting the semiconductor element,
the second layer being one of a semiconductor layer and a metal layer.

21. The semiconductor device of claim 1 , wherein the first and second unit layers have a same width as the first insulation single layer.

Assignees

• Kim Sun-Kook
• Choi Woong
• Jin Yong-Wan
• Samsung Electronics Co Ltd

Inventors

• Kim Sun-Kook
• Choi Woong
• Jin Yong-Wan

Classifications

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/473

  having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT · CPC title

• H10D30/023

  having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031) · CPC title

• H10D30/015

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title

• H10D62/882 Primary

  Graphene · CPC title