Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-8951883-B2
Application number	US-201213345409-A
Country	US
Kind code	B2
Filing date	Jan 6, 2012
Priority date	Aug 24, 2011
Publication date	Feb 10, 2015
Grant date	Feb 10, 2015

Abstract

A semiconductor device and a manufacturing method therefor is based on the fact that a thinner liner oxide layer on the bottom of the trenches can lead to a higher subsequent deposition rate. After forming trenches and a liner oxide layer and before depositing a filling oxide layer in the trenches, a portion of or all of the thickness of the liner oxide layer on bottom of trenches in an isolation area is removed. Removing some or all of a liner oxide layer on the bottom of trenches in an isolation area can improve the deposition rate for trenches in such that the difference in thickness can be reduced for deposited filling oxide layer between isolation area and dense area.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming a nitride layer on a substrate, and forming trenches in an isolation area and trenches in a dense area;
forming a first liner insulating layer in the trenches in the isolation area and in the dense area, including on the bottom and sidewalls of the trenches, wherein the first liner insulating layer is in contact with the substrate;
etching off a portion of or all of the thickness of the first liner insulating layer on the bottom of the trenches in the isolation area, the first liner insulating layer in the dense area remaining unetched during the etching;
depositing a second insulating layer to fill up the trenches in the isolation area and in the dense area; and
with the nitride layer as a blocking layer, planarizing the second insulating layer outside the trenches in the isolation area and in the dense area by a chemical and mechanical planarization process.

2. The method according to claim 1 , wherein removing the first liner insulating layer comprises:
forming a spacer layer over the first liner insulating layer on the sidewalls of the trenches in the isolation area and on the sidewalls and bottom of the trenches in the dense area;
with the spacer layer as a mask, etching the first liner insulating layer on the bottom of the trenches in the isolation area; and
removing the spacer layer.

3. The method according to claim 2 , wherein forming the spacer layer comprises:
coating photoresist in the trenches in the isolation area and in the dense area; and
removing, by a photolithography process, only the photoresist on the bottom of the trenches in the isolation area while the photoresist remains on the sidewalls of the trenches in the isolation area and on the sidewalls and bottom of the trenches in the dense area as the spacer layer.

4. The method according to claim 2 , wherein etching the first liner insulating layer on the bottom of the trenches in the isolation area comprises:
removing a portion of or all of the thickness of the first liner insulating layer on the bottom of the trenches in the isolation area through a wet etching or dry etching process.

5. The method according to claim 1 , wherein the first liner insulating layer comprises an oxide layer.

6. The method according to claim 5 , wherein the first liner insulating layer is formed using middle temperature oxide deposition (MTO).

7. The method according to claim 6 , wherein the first liner insulating layer formed on the bottom and sidewalls of the trenches in the isolation area and in the dense area has a thickness ranging from 10 Å to 100 Å.

8. The method according to claim 1 , wherein the second insulating layer comprises an oxide layer.

9. The method according to claim 8 , wherein the second insulating layer is made of one of high density plasma (HDP) oxides, high aspect ratio process (HARP) based oxides and spin on glass (SOG) based oxides.

10. The method according to claim 1 , wherein the trenches in the isolation area have a width greater than or equal to 1 μm.

11. The method according to claim 2 , wherein the spacer layer over the first liner insulating layer on the sidewalls of the trenches in the isolation area has a thickness ranging from 0.1 to 0.5 μm.

12. The method according to claim 4 , wherein the wet etching process comprises the use of hydrofluoric acid.

13. The method according to claim 1 , wherein in the chemical mechanical planarization process, the second insulating layer has a selectivity rate greater than 5 with respect to the nitride layer.

14. The method according to claim 13 , wherein in the chemical mechanical planarization process, the second insulating layer has a selectivity rate greater than 9 with respect to the nitride layer.

15. The method according to claim 1 , further comprising, after the second insulating layer is deposited, an annealing step after the second insulating layer is deposited to fill up the trenches in the isolation area and in the dense area.

16. The method according to claim 1 , further comprising a step of forming a lining oxide layer on the substrate before the nitride layer is formed.

17. The method according to claim 1 , wherein the first liner insulating layer is conformal to the trenches in the isolation area and the dense area.

Assignees

• Shao Qun
• Hong Zhongshan
• Semiconductor Mfg Int Beijing

Inventors

• Shao Qun
• Hong Zhongshan

Classifications

• H10W10/0143 Primary

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17 Primary

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L21/76229 Primary

  Electricity · mapped topic